METHODS
ASICS Design: design flow in analog mode
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The
circuit is described using a schematic composer or a behavioral
language. |
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Electrical
simulations are run at transistor or behavioral level. |
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Depending on simulations results, the schematic or component parameters may be modified. |
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Edition
of a custom layout to generate the fabrication masks (with Design
Rules Check). |
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The
layout is extracted and checked with the schematic. Parasitic and
process simulations are possible. |
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Layout
of an artificial neuron chips. Fabrication patterns, depending on
the choosen process, are drawn at real scale using a graphical editor. The pattern in this example is for a BiCMOS (Bipolar and MOS transistors) 0.8µm technology from AMS foundry. |
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Silicon
chip die ~20.000 transistors, area = 2450 x 2450 µm². Gold wires interconnect pins of the package to the metallization patterns on the die. |
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A
die is mounted in a package. The resulting IC will be soldered on
a printed circuit board. |
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